Packaged microelectronic devices and methods for packaging microelectronic devices

ABSTRACT

Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

TECHNICAL FIELD

The present invention is related to packaged microelectronic devices and methods for packaging microelectronic devices.

BACKGROUND

Microelectronic devices are used in cell phones, pagers, personal digital assistants, computers, and many other products. A packaged microelectronic device can include a microelectronic die, an interposer substrate or lead frame attached to the die, and a molded casing around the die. The microelectronic die generally has an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads are coupled to terminals on the interposer substrate or lead frame. The interposer substrate can also include ball-pads coupled to the terminals by traces in a dielectric material. An array of solder balls is configured so that each solder ball contacts a corresponding ball-pad to define a “ball-grid” array. Packaged microelectronic devices with ball-grid arrays are generally higher grade packages that have lower profiles and higher pin counts than conventional chip packages that use a lead frame.

Packaged microelectronic devices are typically made by (a) forming a plurality of dies on a semiconductor wafer, (b) cutting the wafer to singulate the dies, (c) attaching individual dies to an interposer substrate, (d) wire-bonding the bond-pads to the terminals of the interposer substrate, and (e) encapsulating the dies with a molding compound. It is time consuming and expensive to mount individual dies to individual interposer substrates. Also, as the demand for higher pin counts and smaller packages increases, it become more difficult to (a) form robust wire-bonds that can withstand the forces involved in molding processes and (b) accurately form other components of die level packaged devices. Therefore, packaging processes have become a significant factor in producing semiconductor and other microelectronic devices.

Another process for packaging microelectronic devices is wafer-level packaging. In wafer-level packaging, a plurality of microelectronic dies are formed on a wafer and then a redistribution layer is formed on top of the dies. The redistribution layer has a dielectric layer, a plurality of ball-pad arrays on the dielectric layer, and traces coupled to individual ball-pads of the ball-pad arrays. Each ball-pad array is arranged over a corresponding microelectronic die, and the ball-pads in each array are coupled to corresponding bond-pads on the die by the traces in the redistribution layer. After forming the redistribution layer on the wafer, a stenciling machine deposits discrete blocks of solder paste onto the ball-pads of the redistribution layer. The solder paste is then reflowed to form solder balls or solder bumps on the ball-pads. After formation of the solder balls on the ball-pads, the wafer can be cut to singulate the dies. Microelectronic devices packaged at the wafer-level can have high pin counts in a small area, but they are not as robust as devices packaged at the die-level.

Packaged microelectronic devices can also be produced by “build-up” packaging. For example, a sacrificial substrate can be attached to a panel including a plurality of microelectronic dies and an organic filler that couples the dies together. The sacrificial substrate is generally a ceramic disc, and it is attached to the active side of the microelectronic dies. Next, the back side of the microelectronic dies is thinned, and then a ceramic layer is attached to the back side. The sacrificial substrate is then removed from the active side of the dies and build-up layers or a redistribution layer can be formed on the active side of the dies. Packaged devices using a build-up approach on a sacrificial substrate provide high pin counts in a small area and a reasonably robust structure.

The build-up packaging process, however, has several drawbacks. For example, the process is relatively expensive and may not be used on equipment set up for circular substrates. Furthermore, the resulting packaged microelectronic devices do not have an effective mechanism for dissipating heat, which can significantly impair the electrical performance of the device. Accordingly, there is a need for an efficient and cost-effective process to package microelectronic dies that have heat dissipation mechanisms.

SUMMARY

The present invention is directed to packaged microelectronic devices and methods for packaging microelectronic devices. One aspect of the invention is directed to a method of packaging a microelectronic device that includes a microelectronic die having an integrated circuit, a first side with a plurality of bond-pads electrically coupled to the integrated circuit, and a second side opposite the first side. In one embodiment, the method includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. In a further aspect of this embodiment, the substrate can include a thermal conductive substrate, such as a substrate comprised of copper, aluminum, or an alloy. In another aspect of this embodiment, the substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

In another embodiment of the invention, the method includes placing the microelectronic die in the recess in the substrate with the second side facing toward the substrate, covering the first side of the microelectronic die with the dielectric layer, and disposing a conductive link in the dielectric layer that is electrically coupled to at least one bond-pad. In a further aspect of this embodiment, the substrate can be a generally circular substrate. In another aspect of this embodiment, the method can further include placing an electrical coupler on the at least one bond-pad of the microelectronic die before covering the first side of the microelectronic die with the dielectric layer.

Another aspect of the invention is directed to a packaged microelectronic device. In one embodiment, the device includes a single, continuous substrate having a recess and a microelectronic die having an integrated circuit, a first side with a plurality of bond-pads electrically coupled to the integrated circuit, and a second side opposite the first side. The microelectronic die is received within the recess with the second side facing the substrate. The device also includes a dielectric layer over the microelectronic die and a ball-pad in or on the dielectric layer. The ball-pad is electrically coupled to one of the plurality of bond-pads. In a further aspect of this embodiment, the substrate can be a thermally conductive substrate. For example, the substrate can include copper, aluminum, or an alloy.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a top plan view of a rectilinear substrate in accordance with one embodiment of the invention.

FIG. 1B is a top plan view of a circular substrate in accordance with another embodiment of the invention.

FIGS. 2-6 illustrate various stages in a method of packaging microelectronic devices in accordance with one embodiment of the invention.

FIG. 2 is a schematic side cross-sectional view of microelectronic devices after microelectronic dies are received in recesses in the substrate.

FIG. 3 is a schematic side cross-sectional view of the microelectronic devices after depositing a dielectric layer and forming vias in the dielectric layer.

FIG. 4 is a schematic side cross-sectional view of the microelectronic devices after forming conductive links.

FIG. 5 is a schematic side cross-sectional view of the microelectronic devices after depositing a second dielectric layer and forming vias in the second dielectric layer.

FIG. 6 is a schematic side cross-sectional view of the microelectronic devices after depositing ball-pads and solder balls.

FIGS. 7-11 illustrate various stages in a method of packaging microelectronic devices in accordance with another embodiment of the invention.

FIG. 7 is a schematic side cross-sectional view of microelectronic devices after microelectronic dies are received in recesses in the substrate and electrical couplers are formed on the dies.

FIG. 8 is a schematic side cross-sectional view of the microelectronic devices after covering the substrate and the microelectronic dies with a first dielectric layer.

FIG. 9 is a schematic side cross-sectional view of the microelectronic devices after forming conductive links.

FIG. 10 is a schematic side cross-sectional view of the microelectronic devices after depositing a second dielectric layer.

FIG. 11 is a schematic side cross-sectional view of the microelectronic devices after depositing ball-pads and solder balls.

DETAILED DESCRIPTION

The following description is directed toward packaged microelectronic devices and methods for packaging microelectronic devices. Many specific details of several embodiments are described below with reference to packaged microelectronic devices having microelectronic dies and a substrate to provide a thorough understanding of such embodiments. The present invention, however, can be practiced using other types of microelectronic devices and/or micromechanical devices. Those of ordinary skill in the art will thus understand that the invention may have additional embodiments, or that the invention may be practiced without several of the details described below.

FIG. 1A is a top plan view of a rectilinear substrate 110 a in accordance with one embodiment of the invention. The rectilinear substrate 110 a has a first surface 111 a with a plurality of recesses 112. The recesses 112 can be arranged in a series of columns 116 a and rows 118 a or in another arrangement. The recesses 112 are shaped to receive one or more microelectronic dies. For example, in the illustrated embodiment, the recesses 112 have a generally rectangular shape. In other embodiments, the recesses 112 can have other shapes. In one aspect of the illustrated embodiment, the recesses 112 can be formed in the substrate 110 a by etching, coining, stamping, or other suitable processes. In another aspect of the embodiment, the substrate 110 a can comprise a thermally conductive material as described in greater detail below.

FIG. 1B is a top plan view of a circular substrate 110 b in accordance with another embodiment of the invention. The circular substrate 110 b has a first surface 111 b with a plurality of recesses 112. The recesses 112 can be arranged in a series of columns 116 b and rows 118 b or in another arrangement. One advantage of the substrate 110 b is that it can be used on equipment set up for circular substrates.

FIGS. 2-6 illustrate various stages in a method of packaging microelectronic devices in accordance with one embodiment of the invention. In the illustrated method, the microelectronic devices are packaged as part of a batch process. In other embodiments, a single microelectronic device can be packaged according to the illustrated method.

FIG. 2 is a schematic side cross-sectional view of microelectronic devices 100 (identified individually as 100 a-b) after microelectronic dies are received in recesses in the substrate. Each microelectronic device 100 can include a portion of a substrate 110, such as a mounting member, having a recess 112 and a microelectronic die 120 (identified individually as 120 a-b) received within the recess 112. The substrate 110 can be similar to the substrate 110 a described above with reference to FIG. 1A or the substrate 110 b described above with reference to FIG. 1B. In one aspect of the illustrated embodiment, an adhesive 130 is deposited into the recesses 112 of the substrate 110 to bond the microelectronic dies 120 to the substrate 110. The adhesive 130 can be deposited into the recesses 112 by placing a volume of adhesive on a first surface 111 of the substrate 110 and moving a wiper blade across the first surface 111 to drive the adhesive 130 into the recesses 112 before placing the dies 120 in the recesses 112. In other embodiments, the adhesive 130 can be deposited into the recesses 112 by other devices, such as by a pin transfer mechanism or screen-printing. In additional embodiments, the microelectronic devices 100 may not include the adhesive 130.

The microelectronic dies 120 are placed into the recesses 112 of the substrate 110 after singulating the dies 120. In one aspect of this embodiment, the microelectronic dies 120 include an integrated circuit 122 (shown schematically), a first side 126 with bond-pads 124 electrically coupled to the integrated circuit 122, and a second side 128 opposite the first side 126. The microelectronic dies 120 are placed into the recesses 112 with the second side 128 facing the substrate 130. The microelectronic dies 120 can be placed into the recesses 112 by conventional die attach equipment. The recesses 112 can have a width D₁ greater than the width D₃ of the microelectronic dies 120 and a depth D₂ greater than the height D₄ of the microelectronic dies 120. Accordingly, the microelectronic dies 120 are received within the recesses 112. In other embodiments, the height of the microelectronic die may exceed the depth of the recess.

FIG. 3 is a schematic side cross-sectional view of the microelectronic devices 100 after depositing a dielectric layer and forming vias in the dielectric layer. After the microelectronic dies 120 are placed in the recesses 112 of the substrate 110, a first dielectric layer 140 a having a thickness T₁ is deposited across the first surface 111 of the substrate 110 and the first sides 126 of the microelectronic dies 120. The dielectric material can also fill the gap in the recesses 112 between the substrate 110 and the microelectronic dies 120. In other embodiments, a filler can be used to fill the gap in the recesses 112 between the substrate 110 and the microelectronic dies 120. After the first dielectric layer 140 a has been deposited, portions of the first dielectric layer 140 a are removed to form vias 150 a over the bond-pads 124 of the microelectronic die 120. More specifically, in the illustrated embodiment, each via 150 a is aligned with a corresponding bond-pad 124. The vias 150 a can be formed in the first dielectric layer 140 a by etching, laser drilling, or other suitable processes.

FIG. 4 is a schematic side cross-sectional view of the microelectronic devices 100 after forming conductive links 160. The conductive links 160 include a horizontal portion 160 a that extends along a first surface 141 of the first dielectric layer 140 a and a vertical portion 160 b in the via 150 a. The vertical portion 160 b of the conductive link 160 electrically couples the horizontal portion 160 a to the bond-pads 124 of the microelectronic die 120. In one aspect of this embodiment, each bond-pad 124 has a corresponding conductive link 160. In another aspect of the illustrated embodiment, the conductive links 160 can be formed by depositing a seed layer and then plating a conductive material onto the seed layer. In other embodiments, the conductive links 160 can be formed through other methods.

FIG. 5 is a schematic side cross-sectional view of the microelectronic devices 100 after depositing a second dielectric layer and forming vias in the second dielectric layer. Once the conductive links 160 are formed on the microelectronic devices 100, a second dielectric layer 140 b having a thickness T₂ is deposited across the substrate 110. In the illustrated embodiment, the second dielectric layer 140 b covers the first dielectric layer 140 a and the conductive links 160. After the second dielectric layer 140 b has been deposited, portions of the layer 140 b are removed to create vias 150 b that extend to the conductive links 160. The vias 150 b can be formed proximate to the ends 161 of the conductive links 160.

FIG. 6 is a schematic side cross-sectional view of the microelectronic devices 100 after depositing ball-pads and solder balls. Once the vias 150 b are formed in the second dielectric layer 140 b, ball-pads 170 are formed in the vias 150 b and then solder balls 180 are deposited onto the ball-pads 170. The solder balls 180 are electrically coupled to the bond-pads 124 of the microelectronic die 120, and thus the solder balls 180, ball-pads 170, and conductive links 160 form a redistribution assembly. In the illustrated embodiment, the solder balls 180 are superimposed over the substrate 110 but not the recesses 112. In other embodiments, the conductive links may have a different length, and accordingly the ball-pads and solder balls can be arranged differently, such as being superimposed over the microelectronic die 120. The substrate 110 can be back ground to reduce the profile of the packaged microelectronic devices 100, and the substrate 110 and dielectric layers 140 a-b can be cut along lines A₁ and A₂ to singulate the microelectronic devices 100. Each microelectronic device 100 can be attached to a printed circuit board or other device. In other embodiments, a microelectronic device can include two or more microelectronic dies to create a higher density microelectronic device.

In one aspect of the microelectronic device 100 illustrated in FIGS. 2-6, the substrate 110 can be thermally conductive to transfer heat from the microelectronic die 120 to an external heat sink (not shown). For example, in one embodiment, the substrate 110 can comprise copper, aluminum, or an alloy (e.g., an NiFe alloy such as alloy 42). In another embodiment, such as in a chip scale package, a substrate can have a coefficient of thermal expansion at least generally similar to the coefficient of thermal expansion of the microelectronic die. In this embodiment, the thermal stress between the microelectronic die and the substrate caused by thermal cycling is reduced because the coefficients of thermal expansion of the substrate and the microelectronic die are similar. In other embodiments, such as those with a larger package, the substrate can have a coefficient of thermal expansion at least generally similar to the coefficient of thermal expansion of a printed circuit board. In these embodiments, the thermal stress between the printed circuitboard and substrate is reduced.

FIGS. 7-11 illustrate various stages in a method of packaging microelectronic devices in accordance with another embodiment of the invention. FIG. 7 is a schematic side cross-sectional view of microelectronic devices 200 after the microelectronic dies 120 are received in recesses in the substrate 110 and electrical couplers 264 are formed on the dies 120. In the illustrated embodiment, the microelectronic devices 200 are generally similar to the microelectronic devices 100 described above with reference to FIG. 2. For example, the microelectronic devices 200 include a substrate 110 having recesses 112 and microelectronic dies 120 received within the recesses 112. The microelectronic devices 200 also include a plurality of electrical couplers 264 deposited on the bond-pads 124 of the microelectronic dies 120. More specifically, the electrical couplers 264 are deposited on a surface 125 of corresponding bond-pads 124. Accordingly, the electrical couplers 264 can be electrically coupled to the integrated circuit 122 of the microelectronic die 120.

FIG. 8 is a schematic side cross-sectional view of the microelectronic devices 200 after covering the substrate 110 and the microelectronic dies 120 with a first dielectric layer 240 a. Once electrical couplers 264 are placed on the bond-pads 124, a first dielectric layer 240 a is deposited across the substrate 110 and the microelectronic dies 120. The first dielectric layer 240 a has a thickness T₃ and can be spun-on or otherwise dispensed onto the substrate 110 and dies 120. The electrical couplers 264 have a height H and can be grounded so that a top surface 266 of the electrical couplers 264 does not project beyond a first surface 241 of the first dielectric layer 240 a.

FIG. 9 is a schematic side cross-sectional view of the microelectronic devices 200 after forming conductive links 260. The conductive links 260 are formed on the first surface 241 of the first dielectric layer 240 a to be in physical contact with corresponding electrical couplers 264. For example, in the illustrated embodiment, the conductive links 260 have a first end 262 positioned at least proximate to the top surface 266 of the electrical couplers 264.

FIG. 10 is a schematic side cross-sectional view of the microelectronic devices 200 after depositing a second dielectric layer 240 b. In one aspect of the illustrated embodiment, the second dielectric layer 240 b is deposited over the first dielectric layer 240 a and the conductive links 260. After depositing the second dielectric layer 240 b, portions of the layer 240 b are removed to create vias 250. In the illustrated embodiment, the vias 250 are formed proximate to a second end 261 of the conductive links 260. In other embodiments, the vias 250 can be formed at other positions along the conductive link 260.

FIG. 11 is a schematic side cross-sectional view of the microelectronic devices 200 after depositing ball-pads 170 and solder balls 180. Once the vias 250 have been formed in the second dielectric layer 240 b, a plurality of ball-pads 170 are formed in the vias 250. Next, a plurality of solder balls 180 are deposited onto corresponding ball-pads 170. In another aspect of this embodiment, the substrate 110 and the dielectric layers 240 a-b can be cut along lines A₃ and A₄ to singulate the microelectronic devices 200.

From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims. 

1-74. (canceled)
 75. A packaged semiconductor device, comprising: a substrate having a substrate surface and a recess extending from the substrate surface into the substrate; a semiconductor die in the recess, the semiconductor die having an integrated circuit and a bond site proximate to the substrate surface; an electric coupler on the bond site of the semiconductor die; a dielectric layer having a first portion over the semiconductor die and the electric coupler and a second portion in the recess of the substrate, the first portion of the dielectric layer having a thickness approximately equal to a height of the electric coupler relative to the substrate surface; and a conductive link on the dielectric layer and in direct contact with the electric coupler.
 76. The packaged semiconductor device of claim 75 wherein the substrate comprises a thermally conductive substrate.
 77. The packaged semiconductor device of claim 75 wherein the substrate comprises at least one of copper and aluminum.
 78. The packaged semiconductor device of claim 75 wherein: the substrate has a first coefficient of thermal expansion; and the semiconductor die has a second coefficient of thermal expansion at least approximately equal to the first coefficient of thermal expansion.
 79. The packaged semiconductor device of claim 75 wherein the substrate has a first coefficient of thermal expansion that is approximately equal to a second coefficient of thermal expansion of a printed circuit board.
 80. The packaged semiconductor device of claim 75 wherein the dielectric layer is a first dielectric layer, and wherein the packaged semiconductor device further comprises: a second dielectric layer on the conductive link and the first dielectric layer, the second dielectric layer having a via proximate to the conductive link; a ball site at least partially in the via; and a solder ball on the ball site.
 81. A packaged semiconductor device, comprising: a substrate having a substrate surface and a recess extending from the substrate surface into the substrate; a semiconductor die in the recess and having an integrated circuit and a bond site proximate to the substrate surface; an electric coupler having a first end contacting the bond site of the semiconductor die and a second end opposite the first end; a dielectric layer having a first portion over the semiconductor die and the electric coupler and a second portion in the recess, the first portion of the dielectric layer having a first surface proximate to the substrate surface and a second surface opposite the first surface, wherein the second end of the electric coupler does not project beyond the second surface of the dielectric layer; and a conductive link on the second surface of the dielectric layer and in electrical communication with the electric coupler.
 82. The packaged semiconductor device of claim 81 wherein the recess has a recess height and the semiconductor die has a die height less than the recess height.
 83. The packaged semiconductor device of claim 81 wherein the second portion of the dielectric material fills a gap in the recess between the substrate and the semiconductor die.
 84. The packaged semiconductor device of claim 81 wherein the electric coupler has a height between the first end and the second end, and wherein the height of the electric coupler is approximately equal to a distance between the first and second surfaces of the dielectric layer.
 85. The packaged semiconductor device of claim 81 wherein the dielectric layer is a first dielectric layer, and wherein the packaged semiconductor device further comprises: a second dielectric layer on the conductive link and the second surface of the first dielectric layer, the second dielectric layer having a via generally aligned with the conductive link; and a ball site in the via and in electrical communication with the conductive link.
 86. The packaged semiconductor device of claim 85 wherein the conductive link having a first end proximate to the electric coupler and a second end extending laterally on the second surface of the first dielectric layer from the first end, and wherein the via is generally aligned with the second end of the conductive link.
 87. The packaged semiconductor device of claim 85 wherein the conductive link having a first end proximate to the electric coupler and a second end extending laterally on the second surface of the first dielectric layer from the first end, and wherein the first end of the conductive link is in physical contact with the second end of the electric coupler.
 88. A packaged semiconductor device, comprising: a substrate having a substrate surface and a recess extending from the substrate surface into the substrate; a semiconductor die in the recess and having a first side with a bond site and a second side opposite the first side; and a redistribution assembly coupled to the substrate, the redistribution assembly having an electric coupler on the bond site of the semiconductor die, a dielectric layer having a first portion over the first side of the semiconductor die and the electric coupler and a second portion in the recess, and a conductive link on the dielectric layer and in physical contact with the electric coupler.
 89. The packaged semiconductor device of claim 88 wherein the electric coupler having a first end on the bond site of the semiconductor die and a second end opposite the first end, and wherein the dielectric layer having a first surface proximate to the substrate surface and a second surface opposite to the first surface, and wherein the second surface of the dielectric layer is generally transversely aligned with the second end of the electric coupler.
 90. The packaged semiconductor device of claim 88 wherein the redistribution assembly further comprises a ball site in electrical communication with the semiconductor die.
 91. The packaged semiconductor device of claim 88 wherein the redistribution assembly further comprises a ball site generally aligned with the conductive link.
 92. The packaged semiconductor device of claim 91 wherein the dielectric layer is a first dielectric layer, and wherein the redistribution assembly further comprises a second dielectric layer on the conductive link and the first dielectric layer, and wherein the second dielectric layer includes a via containing the ball site.
 93. The packaged semiconductor device of claim 88 wherein the redistribution assembly further comprises a ball site in electrical communication with the semiconductor die and a solder ball on the ball site. 